The present invention relates to semiconductor technologies, more particularly to a method of forming a semiconductor device.
With the continuing development of semiconductor technologies, the improvements in the performance of integrated circuits are mainly achieved through shrinking the size of the integrated circuit device and increasing its speed. Currently, because the pursuit of high-density, high performance and low cost in the semiconductor industry has progressed to nano-technology process node, especially when the semiconductor device dimensions have been reduced down to 20 nm or below, semiconductor device fabrication is constrained by a variety of physical limits. Reduced feature sizes cause reduction of the spatial dimensions of the device's structural characteristics. Gaps and groove widths in devices have been narrowed to such a degree that the depth-to-width aspect ratio is high enough to cause difficulty in dielectric gap filling.
In a FinFET process, flowable chemical vapor deposition (Flowable CVD, or FCVD) is usually used in forming an interlayer dielectric layer. In the source/drain region, the SiGe or SiC stress layers formed on the top surfaces of the fins have irregular shapes and their sizes fluctuate widely. The inventors have observed that this causes the gaps between adjacent fins to become narrower, which in turn affects the filling ability of the FCVD interlayer dielectric material, resulting in filling voids, as shown in FIG. 1. Thus, the density of the interlayer dielectric layer is reduced.
Therefore, there is a need for a better manufacturing method.